In high speed binary data serial communications between integrated circuits (systems), it often occurs that the signals transmitted from one integrated circuit to another one cannot be reliably sampled on a predetermined clock signal. In this case, it is common to sample the incoming binary data stream using the n phases of a reference clock signal generated by a multiphase clock generator. Then, an edge detector is used to determine which of the sampled signals is the best candidate to be kept to represent the recovered data for subsequent processing. Such a sampling technique is extensively used in case of high speed asynchronous serial data communications where the clock signal is not transmitted to the receiving device.
This major problem has received a number of solutions so far, such as described in U.S. Pat. No. 5,577,078 which discloses an edge detector wherein the input data signal is coupled to a delay chain that develops delayed versions thereof. Adjacent phase delayed pairs are selected, one pair at a time, and compared to the clock signal to determine if an edge (or transition) of the clock falls between the edges of the data signal in the selected phase pair or outside. In the latter case, the process is repeated on another pair for comparison. With a clock frequency equal to twice data frequency, the data can be sampled on the falling edge of the clock. This edge detector has some disadvantages. First, delay lines are known to be strongly dependent on the manufacturing process (there is often a ratio of 3 between the best and the worst cases). In addition, this circuit has a poor noise immunity and is relatively slow, since it requires a clock frequency equal to twice the data frequency.